Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM memory cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data are stored as charge on solid-state capacitors, and must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, physical scaling of device sizes raises significant issues in connection with such embedded memory.
A problem encountered in connection with embedded SRAM memory now realized by modern manufacturing technology stems from the increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a higher likelihood that one or more cells cannot be read or written as expected.
A particular failure mode that has been observed in conventional modern SRAM memories is the failure related to the switching of the state of an SRAM cell in a read operation. The read operation of an SRAM results in the internal node holding the zero to rise up due to the voltage division along the driver and pass transistor. When the rise is beyond a threshold, it can result in the bit flipping due to regenerative feedback and hence loss of stored data.